Inaddition,bydefiningusescenariosbeforehand,itispossibletonotjustidlebutpower-downlargesectionsoftheSoCmostofthetime.Iftheuserisjustlisteningtotunes,orjustsquintingatavideoclip,muchoftherestofthesystemcanbepoweredoff,leavingonlyenoughinterfacesalivetostreamthemediadataintothehandsetandkeepawatchfuleyeoverthecellularlink.“ApplehasahugeadvantageinpowermanagementbecausetheiPhoneisessentiallyacloseds
In additi
on, by defining use scenarios beforehand, it is possible to not just idle but power-down large sections of the
SoC most of the time. If the user is just listening to tunes, or just squinting at a video clip, much of the rest of the system
canbe powered off, leaving only enough interfaces alive to stream the media data into the handset and keep a watchful eye over the cellular link.
“Apple h
asa huge advantage in power management because the iPhone is essentially a closed system,” Bruce observed. “They can literally try all the allowable use scenarios. That will al
ways give a better power profile than they could achieve with a general-purpose, programmable device.”
In comparison, consider a recently announced Mobilygen EnViE, an H.264 high-profile, high-definition video encoder-decoder (CoDec) SoC. In some ways the block diagram
s of the iPhone system chip and the Molilygen CoDec look remarkably similar—a core of secret sauce surrounded by every interface you could need for a variety of use scenarios, and a carefully crafted pipe to hard-pressed external DRAM. Functionally, as well, each chip faces a combination of interface servicing, system management, data streaming and hard real-time tasks. But of course in detail the two chips differ entirely.
Mobilygen started life thinking ab
outvideo CoDecs in terms of abstract algorithms and software implementation, not in terms of SoC design. That watermark remains in the company’s architectural approach. The heart of the Mobilygen chip is not a cluster of autonomous functional blocks, but a pair of proprietary real-time multi-threading processor cores, according to Mobilygen CTO Sorin Cismas. The multi-thread architecture allows a core to handle a mix of tasks from different functions on the same
CPU, meeting hard real-time deadlines on each task. It also allows the CPUs to be very tolerant of memory latencies, because the cores can simply switch threads—in one cycle, by the way—on a cache miss.
