TISN75LVDS83BLCD屏FlatLink连接方案  2012/3/1

        TI公司的SN75LVDS83B是FlatLink发送器,包括有四个7位并行负载串行输出的移为寄存器,7X时钟合成器,以及5个LVDS线路驱动器,可以把28位单端LVTTL数据同步地在5个平衡对导体上发送,由兼任的接收器接收如SN75LVDS82和集成了LVDS接收器的LCD屏.数据传输速率高达135M像素/秒,像素时肿范围从10MHz到135MHz,工作电压3.3V,75MHz时的功耗为170mW,可用于LCD屏驱动器,UMPC和笔记本电脑以及数码相框等.本文介绍了SN75LVDS83B的主要特性,方框图以及多种连接到LCD屏的应用电路和SN75LVDS83B评估模块电路图.

The SN75LVDS83B FlatLink™ transmitter contains four 7-bit parallel-load serial-outshift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, suchasthe SN75LVDS82 and LCD panels with integrated LVDS receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS83B requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lowerpowerconsumption. A low-level on this signal clears all internal registers to a low-level.

The SN75LVDS83B is characterized for operation over ambient air temperatures of -10℃ to 70℃.

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